This invention relates in general to flipflop circuits, and more particularly, to a flipflop circuit wherein the terminal logic state of the input data signal is latched at the output thereof even if the data and clock signals transition simultaneously thereby avoiding the meta-stable condition.
The conventional flipflop circuit may be found in a myriad of applications and typically includes one or more data inputs, a clock input, and a data output port. The flipflop circuit may operate on either the rising or falling edge of the clock signal (positive or negative edge triggered) for latching the input data signal at the data output thereof. In most if not all applications, the input data signal operates at a much lower frequency and asynchronous with respect to the clock signal. If there is sufficient settling time between the transition of the input data signal and the clock edge, then the output signal latches to the logic state of the input data signal. However, if the data and clock signals change state simultaneously, the flipflop circuit may sample the input data signal at some intermediate level between logic states. The state of the output signal is thus unknown as it may settle to either logic state depending upon the intermediate level of the input data signal at the sample point. This is known as the meta-stable condition and frequently leads to numerous problems during design and afterward in operation. It is desirable to avoid the meta-stable state and always provide a known logic state for the output data signal.
Hence, what is needed is an improved flipflop circuit which avoids the meta-stable condition by providing the terminal logic state of the asynchronous input data signal at the output thereof irrespective of the relative position of the edge of the clock signal.